1. Field of the Invention
This invention relates to a method for forming multi-level contacts, and especially relates to a method for forming multi-level contacts in large scale integration semiconductor devices.
2. Description of the Prior Art
With the advent of Ultra Large Scale Integrated (ULSI) DRAM devices, the size of the memory cells becomes smaller and smaller such that the area available for a single memory cell becomes very small. The manufacture of a DRAM memory cell includes the fabrication of a transistor, a capacitor and contacts to periphery circuits. To shrink the area of the devices in the DRAM cell is thus the most important issue for the designer of the DRAM cell. The stacked capacitor is widely used in DRAM memory cells of small size, because the stacked capacitor occupies relatively small area.
Additionally, as the step height of the stacked capacitor is large for the large-scale integration semiconductor device, multi-level contacts in the periphery circuit are widely used. Also, the self align contact technology must be used in fabricating ULSI devices. When there is no need to use the technology of self align contact, the spacer and the cap of the gate electrode can be formed of TEOS (Tetra Ethyl Ortho Silicate) oxide. As shown in FIG. 1, a plurality of multi-level contact holes is to be formed in the semiconductor device mentioned above.
A silicon substrate 9 is provided for the semiconductor device mentioned above. A plate poly layer 10 is connected to a capacitor 11 of the semiconductor device, and a bit line 13 includes a first tungsten silicide layer 13a and a first poly silicon layer 13b. A word line 17 includes an oxide cap 17a, an oxide spacer 17b, a second tungsten silicide layer 17c, and a second poly silicon layer 17d. The bit line 13 and the word line 17 are used to address a semiconductor device. The plurality of multi-level contact holes 18 is formed penetrating a BPSG layer 19, using a developed photoresist layer 20 as a mask. Because the integration of the semiconductor device mentioned above is not high, it is not necessary to utilize a self-aligned contact technology or an anti-reflection layer. Thus the multi-level contact holes can be formed in an etching step using a fluorine-containing gas as a etchant, such as CCI.sub.2 F.sub.2 or CF.sub.4.
When the large scale integration semiconductor device is to be fabricated, an anti-reflection layer must be used to increase the cell density and improve the photo proximity effect. Typically, an inorganic anti-reflection layer composed of silicon nitride (Si.sub.3 N.sub.4) or silicon oxynitride (SiON) is used. In addition, the technology of self align contact is used to increase critical dimension (CD) control when fabricating the large scale integration semiconductor device. So the material used to form the spacer and the cap of the gate electrode is changed to silicon nitride (Si.sub.3 N.sub.4).
The cross sectional view of the large scale integration semiconductor device is shown in FIG. 2. A silicon substrate 29 is provided for the large scale semiconductor device mentioned above. A plate poly layer 30 is connected to a capacitor 31 of the large scale integration semiconductor device, and a bit line 33 includes a first tungsten silicide layer 33a, a first poly silicon layer 33b, and a silicon oxynitride layer 33c. The silicon oxynitride layer 33c on the first tungsten silicide layer 33a is an anti-reflection layer. A word line 37 includes a silicon nitride layer 37a, a silicon nitride spacer 37b, a second tungsten silicide layer 37c, and a second polysilicon layer 37d. The bit line 33 and the word line 37 are used to address the large scale integration semiconductor device. Subsequently, to form multi-level contacts, a photoresist layer 38 is developed on a BPSG layer 39.
When the traditional fluorine containing gas is used to form the multi-level contact hole, it tends to result in either an etch-stop or/polymer regrowth on both the silicon nitride layer 37a and the silicon oxynitride layer 33c. In addition, silicon loss in the plate poly layer 30 and the silicon substrate 29 can be serious. As shown in FIG. 3, multi-level contact holes 40 are formed in the BPSG layer 39. But as mentioned above, when etching the silicon nitride layer 37a and the silicon oxynitride layer 33c, the etch-stop or the polymer regrowth problems can result. Thus the first tungsten silicide layer 33a and the second tungsten silicide layer 37c are not exposed after the etching step.
Moreover, there is a tendency to over etch the plate poly layer 30 and the silicon substrate 29 when the traditional fluorine-containing gas is used to form the multi-level contact hole to expose the first tungsten silicide layer 33a and the second tungsten silicide layer 37c. The cross sectional view of the semiconductor device processed with the etching step mentioned above is shown in FIG. 3, in which the semiconductor device is defective because of an open circuit or short circuit in the semiconductor device.
Because it is very difficult to use the traditional recipe to form multi-level contact holes of different depth, the yield of the semiconductor device of high integration is low. As the integration of semiconductor gets higher, the multi-level contact becomes more important, and the etching step becomes more critical.